European reference 0 549 623 B1, or respectively, from the corresponding U.S. Pat. No. 5,333,121, a read amplifier according to the preamble of patent claim 1 is known.
In future DRAM memory generations with a memory capacity of 1 Gbit and more, problems with the mismatch of transistors will increase considerably. In principle, variations in the inception voltage and in the drain current are thereby involved, whereby the first make up approx. 65 to 100 percent of the overall effect. The variations in the inception voltage are proportional to 1/.sqroot.gate surface, and consequently increase as the transistor surfaces decrease. The degree of agreement of two transistors required in read amplifiers thus necessarily becomes increasingly worse as progress is made in miniaturization. Previously, the problem was solved above all by increasing the surface of the cross-coupled transistors present in the read amplifier. This procedure will presumably come to an end with 4 GBit memories at the latest, because there the surface required for the cross-coupled transistor pair of the read amplifier exceeds 25 percent of the overall chip surface due to the mismatch problem alone.
From the IEEE Journal of Solid-State Circuits, vol. SC-14, no. 6, December 1979, pages 1066 to 1070, a read amplifier is known that comprises a means for compensation of threshold voltage differences with four MOS transistors. However, this circuit has for example the disadvantage that its compensation effect depends on a relation of circuit-internal capacitors, and remains incomplete.
From the IEEE publication IEDM 1981, pp. 44-47, a read amplifier is known that requires an additional transistor for equalizing the bitlines, and requires an additional connection line for the supply voltage.